Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
26
32072H–AVR32–10/2012
AT32UC3A3
4.4
Programming Model
4.4.1
Register File Configuration
The AVR32UC register file is shown below.
Figure 4-3.
The AVR32UC Register File
4.4.2
Status Register Configuration
The Status Register (SR) is split into two halfwords, one upper and one lower, see
. The lower word contains the C, Z, N, V, and Q condition
code flags and the R, T, and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4.
The Status Register High Halfword
Application
Bit 0
Supervisor
Bit 31
PC
SR
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R3
R1
R2
R0
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
INT0
SP_APP
SP_SYS
R12
R11
R11
R9
R10
R8
Exception
NMI
INT1
INT2
INT3
LR
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Secure
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SEC
LR
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_SP_APP
SS_RAR
SS_RSR
SS_RSR
Bit 31
0
0
0
Bit 16
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 1 Mask
Interrupt Level 3 Mask
Interrupt Level 2 Mask
1
0
0
0
0
1
1
0
0
0
0
0
0
FE
I0M
GM
M1
-
D
M0
EM
I2M
DM
-
M2
LC
1
Initial value
Bit name
I1M
Mode Bit 0
Mode Bit 1
Mode Bit 1
-
Mode Bit 2
Reserved
Reserved
Debug State
-
I3M
Reserved
Exception Mask
Global Interrupt Mask
Debug State Mask
-