Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
287
32072H–AVR32–10/2012
AT32UC3A3
18.7.3
Performance Monitor Memory Map
Note:
1. The number of performance monitors is device specific. If the device has only one perfor-
mance monitor, the Channel1 registers are not available. Please refer to the Module
Configuration section at the end of this chapter for the number of performance monitors on this
device.
Configuration section at the end of this chapter for the number of performance monitors on this
device.
18.7.4
Version Register Memory Map
Note:
1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 18-3.
PDCA Performance Monitor Registers
Offset
Register
Register Name
Access
Reset
0x800
Performance Control Register
PCONTROL
Read/Write
0x00000000
0x804
Channel0 Read Data Cycles
PRDATA0
Read-only
0x00000000
0x808
Channel0 Read Stall Cycles
PRSTALL0
Read-only
0x00000000
0x80C
Channel0 Read Max Latency
PRLAT0
Read-only
0x00000000
0x810
Channel0 Write Data Cycles
PWDATA0
Read-only
0x00000000
0x814
Channel0 Write Stall Cycles
PWSTALL0
Read-only
0x00000000
0x818
Channel0 Write Max Latency
PWLAT0
Read-only
0x00000000
0x81C
Channel1 Read Data Cycles
PRDATA1
Read-only
0x00000000
0x820
Channel1 Read Stall Cycles
PRSTALL1
Read-only
0x00000000
0x824
Channel1 Read Max Latency
PRLAT1
Read-only
0x00000000
0x828
Channel1 Write Data Cycles
PWDATA1
Read-only
0x00000000
0x82C
Channel1 Write Stall Cycles
PWSTALL1
Read-only
0x00000000
0x830
Channel1 Write Max Latency
PWLAT1
Read-only
0x00000000
Table 18-4.
PDCA Version Register Memory Map
Offset
Register
Register Name
Access
Reset
0x834
Version Register
VERSION
Read-only
-