Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and
CFGx.RELOAD_DS registers (see 

Note:

Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is 
required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the max-
imum value, use Row 10 of 

and setup the LLI.SARx address of the 

block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the 
LLI.DARx address of the block descriptor to be equal to the end DARx address of the previous 
block.

At the end of every block transfer, an end of block interrupt is asserted if:

• interrupts are enabled, CTLx.INT_EN = 1

• the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number.

Note:

The block complete interrupt is generated at the completion of the block transfer to the destination.

For rows 6, 8, and 10 of 

, the DMA transfer does not stall between block

transfers. For example, at the end of block N, the DMACA automatically proceeds to block N + 1.

For rows 2, 3, 4, 7, and 9 of 

 (SARx and/or DARx auto-reloaded between

block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted
if the end of block interrupt is enabled and unmasked. 

The DMACA does not proceed to the next block transfer until a write to the block interrupt clear
register, ClearBlock[n], is performed by software. This clears the channel block complete
interrupt.

For rows 2, 3, 4, 7, and 9 of 

 (SARx and/or DARx auto-reloaded between

block transfers), the DMA transfer does not stall if either:

• interrupts are disabled, CTLx.INT_EN = 0, or 

• the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number.

Channel suspension between blocks is used to ensure that the end of block ISR (interrupt ser-
vice routine) of the next-to-last block is serviced before the start of the final block commences.
This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits
b e f o r e   c o m p l e t i o n   o f  t h e   f i n a l   b l o c k .   T h e   r e l o a d   b i t s   C F G x . R E L O A D _ S R   a n d / o r
CFGx.RELOAD_DS should be cleared in the ‘end of block ISR’ for the next-to-last block
transfer.

All multi-block transfers must end as shown in either Row 1 or Row 5 of 

At the end of every block transfer, the DMACA samples the row number, and if the DMACA is in
Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA trans-
fer is terminated.

Note:

Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in 
Row 5 state enables status fetch  for the last block. Ending in Row 1 state disables status fetch for 
the last block.

For rows 2,3 and 4 of 

, (LLPx = 0 and CFGx.RELOAD_SR and/or

C F G x . R E L O A D _ D S   i s   s e t ) ,   m u l t i - b l o c k   D M A   t r a n s f e r s   c o n t i n u e   u n t i l   b o t h   t h e
CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be