Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
384
32072H–AVR32–10/2012
AT32UC3A3
responding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not
drive the line.
drive the line.
The level driven on an I/O line can be determined by writing to the Output Value Register (OVR).
20.5.1.4
Inputs
The level on each I/O line can be read through the Pin Value Register (PVR). This register indi-
cates the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an
external component. Note that due to power saving measures, the PVR register can only be
read when GPER is written to one for the corresponding pin or if interrupt is enabled for the pin.
cates the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an
external component. Note that due to power saving measures, the PVR register can only be
read when GPER is written to one for the corresponding pin or if interrupt is enabled for the pin.
20.5.1.5
Output line timings
The figure below shows the timing of the I/O line when writing a one and a zero to OVR. The
same timing applies when performing a ‘set’ or ‘clear’ access, i.e., writing a one to the Output
Value Set Register (OVRS) or the Output Value Clear Register (OVRC). The timing of PVR is
also shown.
same timing applies when performing a ‘set’ or ‘clear’ access, i.e., writing a one to the Output
Value Set Register (OVRS) or the Output Value Clear Register (OVRC). The timing of PVR is
also shown.
Figure 20-3. Output Line Timings
20.5.2
Advanced Operation
20.5.2.1
Pull-up resistor control
Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled
or disabled by writing a one or a zero to the corresponding bit in the Pull-up Enable Register
(PUER). Control of the pull-up resistor is possible whether an I/O line is controlled by a periph-
eral or the GPIO.
or disabled by writing a one or a zero to the corresponding bit in the Pull-up Enable Register
(PUER). Control of the pull-up resistor is possible whether an I/O line is controlled by a periph-
eral or the GPIO.
20.5.2.2
Input glitch filter
Optional input glitch filters can be enabled on each I/O line. When the glitch filter is enabled, a
glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with dura-
tion of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock
cycles, the pulse may or may not be taken into account, depending on the precise timing of its
occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for
a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces
2 clock cycles of latency.
glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with dura-
tion of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock
cycles, the pulse may or may not be taken into account, depending on the precise timing of its
occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for
a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces
2 clock cycles of latency.
The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit is written
to one in GFER, the glitch filter on the corresponding pin is enabled. The glitch filter affects only
interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the
glitch filters.
to one in GFER, the glitch filter on the corresponding pin is enabled. The glitch filter affects only
interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the
glitch filters.
PB Access
PB Access
CLK_GPIO
Write OVR to 1
Write OVR to 0
OVR / I/O Line
PVR