Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
43
32072H–AVR32–10/2012
AT32UC3A3
7.4
Product Dependencies
7.4.1
I/O Lines
The PM provides a number of generic clock outputs, which can be connected to output pins,
multiplexed with I/O lines. The user must first program the I/O controller to assign these pins to
their peripheral function. If the I/O pins of the PM are not used by the application, they can be
used for other purposes by the I/O controller.
multiplexed with I/O lines. The user must first program the I/O controller to assign these pins to
their peripheral function. If the I/O pins of the PM are not used by the application, they can be
used for other purposes by the I/O controller.
7.4.2
Interrupt
The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using
the PM interrupt requires the interrupt controller to be programmed first.
the PM interrupt requires the interrupt controller to be programmed first.
7.5
Functional Description
7.5.1
Slow Clock
The slow clock is generated from an internal RC oscillator which is always running, except in
Static mode. The slow clock can be used for the main clock in the device, as described in
Static mode. The slow clock can be used for the main clock in the device, as described in
. The slow clock is also used for the Watchdog Timer and measuring various delays in
the Power Manager.
The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running.
The RC oscillator operates at approximately 115 kHz. Software can change RC oscillator cali-
bration through the use of the RCCR register. Please see the Electrical Characteristics section
for details.
The RC oscillator operates at approximately 115 kHz. Software can change RC oscillator cali-
bration through the use of the RCCR register. Please see the Electrical Characteristics section
for details.
RC oscillator can also be used as the RTC clock when crystal accuracy is not required.
7.5.2
Oscillator 0 and 1 Operation
The two main oscillators are designed to be used with an external crystal and two biasing capac-
itors, as shown in
itors, as shown in
. Oscillator 0 can be used for the main clock in the
. Both oscillators can be used as source for the generic
clocks, as described in
.
The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and
XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an
external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a
general purpose I/O.
XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an
external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a
general purpose I/O.
The oscillators can be enabled by writing to the OSCnEN bits in MCCTRL. Operation mode
(external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are
automatically switched off in certain sleep modes to reduce power consumption, as described in
(external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are
automatically switched off in certain sleep modes to reduce power consumption, as described in
.
After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscil-
lators may need a certain amount of time to stabilize on the correct frequency. This start-up time
can be set in the OSCCTRLn register.
lators may need a certain amount of time to stabilize on the correct frequency. This start-up time
can be set in the OSCCTRLn register.
The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks
propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared
according to the status of the oscillators. A zero to one transition on these bits can also be con-
figured to generate an interrupt, as described in
propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared
according to the status of the oscillators. A zero to one transition on these bits can also be con-
figured to generate an interrupt, as described in