Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

TWI transfers require the slave to acknowledge each received data byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not
acknowledge the data byte. As with the other status bits, an interrupt can be generated if
enabled in the Interrupt Enable Register (IER).

TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.

The end of a command is marked when the TWIM sets the SR.CCOMP bit. See 

 and

Figure 23-6. Master Write with One Data Byte

Figure 23-7. Master Write with Multiple Data Bytes

A START condition is transmitted and master receiver mode is initiated when the bus is free and
CMDR has been written with START=1 and READ=1. START and SADR+R will then be trans-
mitted. During the address acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master
polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in
the Status Register if no slave acknowledges the address. 

After the address phase, the following is repeated:

while (NBYTES>0)

TWD

SR.IDLE

TXRDY

Write THR (DATA)

NBYTES set to 1

STOP sent automatically

(ACK received and NBYTES=0)

S

DADR

W

A

DATA

A

P

TWD

SR.IDLE

TXRDY

Write THR 

(DATAn)

NBYTES set to n

STOP sent automatically

(ACK received and NBYTES=0)

S

DADR

W

A

DATAn

A

DATAn+5

A

A

DATAn+m

P

Write THR 

(DATAn+1)

Write THR 

(DATAn+m)

Last data sent