Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

Atmel

产品代码

AT32UC3A3-XPLD

491

32072H–AVR32–10/2012

AT32UC3A3

23.9.1

Control Register

Name:

CR

Access Type:

Write-only

Offset:

0x00

Reset Value:

0x00000000

• STOP: Stop the Current Transfer

Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are

additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully

sent.

Writing a zero to this bit has no effect.

• SWRST: Software Reset

If the TWIM master interface is enabled, writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly

violating the bus semantics.

If the TWIM master interface is not enabled, it must first be enabled before writing a one to this bit.

Writing a zero to this bit has no effect.

• SMDIS: SMBus Disable

Writing a one to this bit disables SMBus mode.

Writing a zero to this bit has no effect.

• SMEN: SMBus Enable

Writing a one to this bit enables SMBus mode.

Writing a zero to this bit has no effect.

• MDIS: Master Disable

Writing a one to this bit disables the master interface.

Writing a zero to this bit has no effect.

• MEN: Master Enable

Writing a one to this bit enables the master interface.

Writing a zero to this bit has no effect.

31

30

29

28

27

26

25

24

-

-

-

-

-

-

-

-

23

22

21

20

19

18

17

16

-

-

-

-

-

-

-

-

15

14

13

12

11

10

9

8

-

-

-

-

-

-

-

STOP

7

6

5

4

3

2

1

0

SWRST

- SMDIS

SMEN

-

-

MDIS

MEN