Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

enabled by default, and can be disabled by writing a one to the Parity Disable bit in the LIN
Mode register (LINMR.PARDIS).

• LINMR.PARDIS=0: During header transmission, the parity bits are computed and in the shift 

register they replace bits 6 and 7 from LINIR.IDCHR. During header reception, the parity bits 
are checked and can generate a LIN Identifier Parity Error (see 

and 7 in LINIR.IDCHR read as zero when receiving.

• LINMR.PARDIS=1: During header transmission, all the bits in LINIR.IDCHR are sent on the 

bus. During header reception, all the bits in LINIR.IDCHR are updated with the received 
Identifier.

After an identifier transaction, a LIN response mode must be selected. This is done in the Node
Action field (LINMR.NACT). Below are some response modes exemplified in a small LIN cluster:

• Response, from master to slave1:

Master: NACT=PUBLISH

Slave1: NACT=SUBSCRIBE

Slave2: NACT=IGNORE

• Response, from slave1 to master:

Master: NACT=SUBSCRIBE

Slave1: NACT=PUBLISH

Slave2: NACT=IGNORE

• Response, from slave1 to slave2:

Master: NACT=IGNORE

Slave1: NACT=PUBLISH

Slave2: NACT=SUBSCRIBE

The response data length is the number of data fields (bytes), excluding the checksum.

Figure 25-31. Response Data Length

The response data length can be configured, either by the user, or automatically by bits 4 and 5
in the Identifier (LINIR.IDCHR), in accordance to LIN 1.1. The user selects one of these modes
by writing to the Data Length Mode bit (LINMR.DLM):

• LINMR.DLM=0: the response data length is configured by the user by writing to the 8-bit Data 

Length Control field (LINMR.DLC). The response data length equals DLC + 1 bytes.

User configuration: 1 - 256 data fields (DLC+1)

Identifier configuration: 2/4/8 data fields

Sync

Break

Sync

Field

Identifier

Field

Checksum

Field

Data
Field

Data
Field

Data
Field

Data
Field