Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

MR

Read-write

0x04

0x00000000  

This register can only be written if write protection is disabled in the 

(WPMR.WPEN is zero).

0: The start frame delimiter is a command or data sync, as defined by MODSYNC.

1: The start frame delimiter is a normal start bit, as defined by MODSYNC.

0: The manchester start bit is either a 0-to-1 transition, or a data sync.

1: The manchester start bit is either a 1-to-0 transition, or a command sync.

0: Manchester endec is disabled.

1: Manchester endec is enabled.

0: The USART does not filter the receive line.

1: The USART filters the receive line by doing three consecutive samples and uses the majority value.

This field determines the number of acceptable consecutive NACKs when in protocol T=0. 

0: Sync pattern according to MODSYNC.

1: Sync pattern according to THR.TXSYNH.

0: NACKs are handled as normal, unless disabled by INACK.

1: The receiver restricts the amount of consecutive NACKs by MAX_ITERATION value. If MAX_ITERATION=0 no NACK will be 

issued and the first erroneous message is accepted as a valid character, setting CSR.ITER.

0: The NACK is generated.

1: The NACK is not generated. 

0: Oversampling at 16 times the baud rate.

1: Oversampling at 8 times the baud rate.

0: The USART does not drive the CLK pin.

1: The USART drives the CLK pin unless USCLKS selects the external clock.

31

30

29

28

27

26

25

24

ONEBIT

MODSYNC

MAN

FILTER

–

MAX_ITERATION

23

22

21

20

19

18

17

16

–

VAR_SYNC

DSNACK

INACK

OVER

CLKO

MODE9

MSBF/CPOL

15

14

13

12

11

10

9

8

CHMODE

NBSTOP

PAR

SYNC/CPHA

7

6

5

4

3

2

1

0

CHRL

USCLKS

MODE