Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
600
32072H–AVR32–10/2012
AT32UC3A3
25.7.4
Interrupt Disable Register
Name:
IDR
Access Type:
Write-only
Offset:
0x0C
Reset Value:
0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identifier Parity Error
• LINISFE: LIN Inconsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Input Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
• LINCE: LIN Checksum Error
• LINIPE: LIN Identifier Parity Error
• LINISFE: LIN Inconsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Input Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has
the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
31
30
29
28
27
26
25
24
–
–
LINSNRE
LINCE
LINIPE
LINISFE
LINBE
MANEA
23
22
21
20
19
18
17
16
–
–
–
MANE
CTSIC
DCDIC
DSRIC
RIIC
15
14
13
12
11
10
9
8
LINTC
LINIR
NACK
RXBUFF
–
ITER/UNRE
TXEMPTY
TIMEOUT
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
–
–
RXBRK
TXRDY
RXRDY