Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the
following host requests will be performed using the default device address 0.

The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to
zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend
state 3ms later.

The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
When the host controller detects a non-idle state on the USB bus, it set the Host Wake-Up inter-
rupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K
state), the Upstream Resume Received Interrupt (RXRSMI) bit in UHINT is set. The user has to
generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send
USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before
writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no
effect.

A control transaction is composed of three stages:

• SETUP

• Data (IN or OUT)

• Status (OUT or IN)

The user has to change the pipe token according to each stage.

For the control pipe, and only for it, each token is assigned a specific initial data toggle
sequence:

• SETUP: Data0

• IN: Data1

• OUT: Data1

IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read which acknowledges or not the bank when it is empty.

The pipe must be configured first.

When the host requires data from the device, the user has to select beforehand the IN request
mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):

• When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before 

freezing the pipe.

• When INMODE is written to one, the USBB will perform IN requests endlessly when the pipe 

is not frozen by the user.

The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE)
field in UPCONn is zero).

The Received IN Data Interrupt (RXINI) bit in UPSTAn is set at the same time as the FIFO Con-
trol (FIFOCON) bit in UPCONn when the current bank is full. This triggers a PnINT interrupt if the
Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one.