Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

UDINT

Read-Only

0x0004

0x00000000

This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.

This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.

This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is 

one.

This bit is cleared when the interrupt source is serviced.

This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is 

one.

This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be 

enabled before).

This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if 

EORSME is one.

This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.

This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This 

triggers an interrupt if WAKEUPE is one.

This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be 

enabled before).

This bit is cleared when the Suspend (SUSP) interrupt bit is set.

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one. 

This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.

31

30

29

28

27

26

25

24

DMA7INT

DMA6INT

DMA5INT

DMA4INT

DMA3INT

DMA2INT

DMA1INT

-

23

22

21

20

19

18

17

16

-

-

-

-

EP7INT

EP6INT

EP5INT

EP4INT

15

14

13

12

11

10

9

8

EP3INT

EP2INT

EP1INT

EP0INT

-

-

-

-

7

6

5

4

3

2

1

0

-

UPRSM

EORSM

WAKEUP

EORST

SOF

MSOF

SUSP