Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

UERST

Read/Write

0x001C

0x00000000

Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus 

reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration 

(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).

All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field 

(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).

The endpoint configuration remains active and the endpoint is still enabled.

Writing a zero to this bit will complete the reset operation and start using the FIFO.

This bit is cleared upon receiving a USB reset.

1: The endpoint n is enabled.

0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint 

n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).

31

30

29

28

27

26

25

24

-

-

-

-

-

-

-

-

23

22

21

20

19

18

17

16

EPRST7

EPRST6

EPRST5

EPRST4

EPRST3

EPRST2

EPRST1

EPRST0

15

14

13

12

11

10

9

8

-

-

-

-

-

-

-

-

7

6

5

4

3

2

1

0

EPEN7

EPEN6

EPEN5

EPEN4

EPEN3

EPEN2

EPEN1

EPEN0