Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

UPSTAn, n in [0..7]

Read-Only

0x0530 + (n * 0x04)

0x00000000

This field contains the byte count of the FIFO.

For OUT pipe, incremented after each byte written by the user into the pipe and decremented after each byte sent to the 

peripheral.

For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user from 

the pipe.

This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

This bit is set/cleared when the UPCFGn.ALLOC bit is set.

This bit is set if the pipe n number of banks (UPCFGn.PBK) and size (UPCFGn.PSIZE) are correct compared to the maximal 

allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size).

If this bit is cleared, the user should rewrite correct values ot the PBK and PSIZE field in the UPCFGn register.

For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.

For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO.

This bit is cleared otherwise.

This bit is also cleared when the RXSTALL or the PERR bit is one.

For non-control pipe, this field indicates the number of the current bank.

31

30

29

28

27

26

25

24

-

PBYCT[10:4]

23

22

21

20

19

18

17

16

PBYCT[3:0]

-

CFGOK

-

RWALL

15

14

13

12

11

10

9

8

CURRBK

NBUSYBK

-

-

DTSEQ

7

6

5

4

3

2

1

0

SHORT

PACKETI

RXSTALLDI/

CRCERRI

OVERFI

NAKEDI

PERRI

TXSTPI/

UNDERFI

TXOUTI

RXINI

0

0

Bank0