Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
791
32072H–AVR32–10/2012
AT32UC3A3
29.3
Block Diagram
Figure 29-1. ADC Block Diagram
29.4
I/O Lines Description
29.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
below.
29.5.1
I/O Lines
The TRIGGER pin may be shared with other peripheral functions through the I/O Controller.
Table 29-1.
ADC Pins Description
Pin Name
Description
VDDANA
Analog power supply
AD[0] - AD[
7]
Analog input channels
TRIGGER
External trigger
AD-
AD-
AD-
Dedicated
Analog
Inputs
AD-
AD-
AD-
Analog Inputs
Multiplexed
With I/O lines
GND
VDDANA
TRIGGER
Trigger
Selection
VREF
Successive
Approximation
Register
Analog-to-Digital
Converter
User
Interface
Control
Logic
ADC
Timer
Counter
Channels
ADC Interrupt
Interrupt
Controller
Peripheral
DMA
Controller
High Speed
Bus (HSB)
Peripheral Bridge
Peripheral Bus
(PB)
I/O
Controller