Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表

32072H–AVR32–10/2012

Figure 10-1. INTC Block Diagram

In order to use this module, other parts of the system must be configured correctly, as described
below.

If the CPU enters a sleep mode that disables CLK_SYNC, the INTC will stop functioning and
resume operation after the system wakes up from sleep mode.

The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager.

The INTC sampling logic runs on a clock which is stopped in any of the sleep modes where the
system RC oscillator is not running. This clock is referred to as CLK_SYNC. This clock is
enabled at reset, and only turned off in sleep modes where the system RC oscillator is stopped.

When an external debugger forces the CPU into debug mode, the INTC continues normal
operation.

All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt
Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that
is active. If several IREQs within the same group are active, the interrupt service routine must
prioritize between them. All of the input lines in each group are logically ORed together to form
the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.

The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to
INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding

Request 
Masking

OR

IREQ0

IREQ1

IREQ2

IREQ31

GrpReq0

Masks

SREG 
Masks

I[3-0]M

GM

INTLEVEL

AUTOVECTOR

Pr

ior

itiz

er

CPU

Interrupt Controller

OR

GrpReqN

NMIREQ

OR

IREQ32

IREQ33

IREQ34

IREQ63

GrpReq1

IRR Registers

IPR Registers

ICR Registers

INT_level, 

offset

INT_level, 

offset

INT_level, 

offset

IPR0

IPR1

IPRn

IRR0

IRR1

IRRn

ValReq0

ValReq1

ValReqN

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