Linear Technology LTC2140-12: 12-bit 25Msps Dual ADC, DDR LVDS Outputs, 5-140MHz, req DC890, LVDS_XFMR and DC1075 DC1620 DC1620A-R 数据表
产品代码
DC1620A-R
1
21421012fa
LTC2142-12/
LTC2141-12/LTC2140-12
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
12-Bit, 65Msps/
40Msps/25Msps Low Power
Dual ADCs
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multi-Channel Data Acquisition
n
Nondestructive Testing
n
2-Channel Simultaneously Sampling ADC
n
70.8dB SNR
n
89dB SFDR
n
Low Power: 92mW/65mW/48mW Total
46mW/33mW/24mW per Channel
n
Single 1.8V Supply
n
CMOS, DDR CMOS, or DDR LVDS Outputs
n
Selectable Input Ranges: 1V
P-P
to 2V
P-P
n
750MHz Full Power Bandwidth S/H
n
Optional Data Output Randomizer
n
Optional Clock Duty Cycle Stabilizer
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
n
64-Pin (9mm × 9mm) QFN Package
The LTC
®
2142-12/LTC2141-12/LTC2140-12 are 2-channel
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.8dB SNR and
89dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08ps
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.8dB SNR and
89dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.3LSB
and no missing codes over temperature. The transition
noise is 0.3LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Technology Corporation. All other trademarks are the property of their respective owners.
2-Tone FFT, f
IN
= 70MHz and 69MHz
CMOS,
DDR CMOS
OR
DDR LVDS
OUTPUTS
DDR CMOS
OR
DDR LVDS
OUTPUTS
1.8V
V
DD
1.8V
OV
DD
CLOCK
CONTROL
D1_11
D1_0
21421012 TA01a
CH 1
ANALOG
INPUT
OUTPUT
DRIVERS
t
t
t
GND
OGND
S/H
12-BIT
ADC CORE
CH 2
ANALOG
INPUT
S/H
12-BIT
ADC CORE
D2_11
D2_0
t
t
t
65MHz
CLOCK
CLOCK
FREQUENCY (MHz)
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21821012 TA01b
FREQUENCY (MHz)
21821012 TA01b
0
10
20
30