Linear Technology LTC2143-14: 14-bit 80Msps Dual ADC, DDR LVDS Outputs, 5-140MHz, req DC890, LVDS_XFMR and DC1075 DC1620 DC1620A-I 数据表
产品代码
DC1620A-I
1
21454314fa
LTC2145-14/
LTC2144-14/LTC2143-14
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
14-Bit, 125Msps/105Msps/
80Msps Low Power Dual ADCs
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multi-Channel Data Acquisition
n
Nondestructive Testing
n
Two-Channel Simultaneously Sampling ADC
n
73.1dB SNR
n
90dB SFDR
n
Low Power: 189mW/149mW/113mW Total
95mW/75mW/57mW per Channel
n
Single 1.8V Supply
n
CMOS, DDR CMOS, or DDR LVDS Outputs
n
Selectable Input Ranges: 1V
P-P
to 2V
P-P
n
750MHz Full Power Bandwidth S/H
n
Optional Data Output Randomizer
n
Optional Clock Duty Cycle Stabilizer
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
n
64-Pin (9mm × 9mm) QFN Package
The LTC
®
2145-14/LTC2144-14/LTC2143-14 are 2-channel
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.1dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08ps
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.1dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.2LSB
and no missing codes over temperature. The transition
noise is 1.2LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Technology Corporation. All other trademarks are the property of their respective owners.
64k Point 2-Tone FFT, f
IN
= 69MHz,
70MHz, –1dBFS, 125Msps
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
DDR CMOS
OR DDR LVDS
OUTPUTS
1.8V
V
DD
1.8V
OV
DD
CLOCK
CONTROL
D1_13
D1_0
21454314 TA01a
CH 1
ANALOG
INPUT
OUTPUT
DRIVERS
t
t
t
GND
OGND
S/H
14-BIT
ADC CORE
CH 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
D2_13
D2_0
t
t
t
125MHz
CLOCK
FREQUENCY (MHz)
–100
–110
–120
–120
–70
–60
–80
–90
AMPLITUDE (dBFS)
–50
–30
–40
–20
–10
0
21454314 TA03b
0
10
20
30
40
50
60