Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 数据表
产品代码
ATEVK1105
429
AT32UC3A
28.8.4
SDRAMC High Speed Register
Register Name
:
HSR
Access Type
:
Read/Write
•
DA: Decode Cycle Enable
A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.
The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
0: Decode cycle is disabled.
1: Decode cycle is enabled.
The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
0: Decode cycle is disabled.
1: Decode cycle is enabled.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
DA
32058K
AVR32-01/12