Atmel SAM4L Xplained Pro Evaluation Kit Atmel ATSAM4L-XPRO ATSAM4L-XPRO 数据表
产品代码
ATSAM4L-XPRO
456
42023E–SAM–07/2013
ATSAM4L8/L4/L2
prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corre-
sponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of
sponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of
where f
CS
is the frequency of the selected clock source.
The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the
prescaler has a 0-to-1 transition.
prescaler has a 0-to-1 transition.
Because of synchronization, the transfer of the INSEL value will not happen immediately. When
changing/setting the INSEL value, the user must make sure that the prescaler bit number INSEL
will not have a 0-to-1 transition before the INSEL value is transferred to the register. In that case,
the first periodic interrupt after the change will not be triggered.
changing/setting the INSEL value, the user must make sure that the prescaler bit number INSEL
will not have a 0-to-1 transition before the INSEL value is transferred to the register. In that case,
the first periodic interrupt after the change will not be triggered.
19.5.3.2
Alarm Interrupt
The AST can also generate alarm interrupts. If the ALARMn bit in IMR is one, the AST will gen-
erate an interrupt request when the counter value matches the selected alarm value, when the
AST is enabled. The alarm value is selected by writing the value to the VALUE field in the corre-
sponding Alarm Register (ARn.VALUE).
erate an interrupt request when the counter value matches the selected alarm value, when the
AST is enabled. The alarm value is selected by writing the value to the VALUE field in the corre-
sponding Alarm Register (ARn.VALUE).
The corresponding ALARMn bit in SR will be set when the counter reaches the selected alarm
value.
value.
Because of synchronization, the transfer of the alarm value will not happen immediately. When
changing/setting the alarm value, the user must make sure that the counter will not count the
selected alarm value before the value is transferred to the register. In that case, the first alarm
interrupt after the change will not be triggered.
changing/setting the alarm value, the user must make sure that the counter will not count the
selected alarm value before the value is transferred to the register. In that case, the first alarm
interrupt after the change will not be triggered.
If the Clear on Alarm bit in the Control Register (CR.CAn) is one, the corresponding alarm inter-
rupt will clear the counter and set the OVF bit in the Status Register. This will generate an
overflow interrupt if the OVF bit in IMR is set.
rupt will clear the counter and set the OVF bit in the Status Register. This will generate an
overflow interrupt if the OVF bit in IMR is set.
19.5.4
Peripheral Events
The AST can generate a number of peripheral events:
• OVF
• PER0
• ALARM0
The PERn peripheral event(s) is generated the same way as the PER interrupt, as described in
. The ALARMn peripheral event(s) is generated the same way as the ALARM
interrupt, as described in
. The OVF peripheral event is generated the same
way as the OVF interrupt, as described in
The peripheral event will be generated if the corresponding bit in the Event Mask (EVM) register
is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable
is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable
f
PA
f
CS
2
INSEL
1
+
-------------------------
=