Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO 数据表
产品代码
ATSAMD21-XPRO
801
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.5.4 Host Frame Number Register
Name:
FNUM
Offset:
0x10
Reset:
0x0000
Property:
Write-Protected
Property:
z
Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 13:3 – FNUM: Frame Number
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the
FNUM field takes its new value.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register
may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or
half-word-wise (16-bits).
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the
FNUM field takes its new value.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register
may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or
half-word-wise (16-bits).
z
Bits 2:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit
15
14
13
12
11
10
9
8
FNUM[10:5]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
FNUM[4:0]
Access
R/W
R/W
R/W
R/W
R/W
R
R
R
Reset
0
0
0
0
0
0
0
0