Linear Technology LTC6957HMS-4 Demoboard:Low Phase Noise, Dual Output Buffer/Driver/Logic Converter with Complementary CMOS Outputs Linear DC1766A-B 数据表
产品代码
DC1766A-B
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
1
6957f
Typical applicaTion
FeaTures
DescripTion
Low Phase Noise, Dual
Output Buffer/Driver/
Logic Converter
The
LTC
®
/
a family of very low phase noise, dual output AC signal
buffer/driver/logic level translators. The input signal can
be a sine wave or any logic level (≤2V
P-P
). There are four
members of the family that differ in their output logic
signal type as follows:
LTC6957-1: LVPECL Logic Outputs
LTC6957-2: LVDS Logic Outputs
LTC6957-3: CMOS Logic, In-Phase Outputs
LTC6957-4: CMOS Logic, Complementary Outputs
The LTC6957 will buffer and distribute any logic signal
LTC6957-1: LVPECL Logic Outputs
LTC6957-2: LVDS Logic Outputs
LTC6957-3: CMOS Logic, In-Phase Outputs
LTC6957-4: CMOS Logic, Complementary Outputs
The LTC6957 will buffer and distribute any logic signal
with minimal additive noise, however, the part really ex-
cels at translating sine wave signals to logic levels. The
early amplifier stages have selectable lowpass filtering
to minimize the noise while still amplifying the signal to
increase its slew rate. This input stage filtering/noise limit-
ing is especially helpful in delivering the lowest possible
phase noise signal with slow slewing input signals such
as a typical 10MHz sine wave system reference.
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents 7969189 and 8319551.
Additive Phase Noise at 100MHz
applicaTions
n
Low Phase Noise Buffer/Driver
n
Optimized Conversion of Sine Wave Signals to
Logic Levels
n
Three Logic Output Types Available
–
LVPECL
–
LVDS
–
CMOS
n
Additive Jitter 45fs
RMS
(LTC6957-1)
n
Frequency Range Up to 300MHz
n
3.15V to 3.45V Supply Operation
n
Low Skew 3ps Typical
n
Fully Specified from –40°C to 125°C
n
12-Lead MSOP and 3mm × 3mm DFN Packages
n
System Reference Frequency Distribution
n
High Speed ADC, DAC, DDS Clock Driver
n
Military and Secure Radio
n
Low Noise Timing Trigger
n
Broadband Wireless Transceiver
n
High Speed Data Acquisition
n
Medical Imaging
n
Test and Measurement
OFFSET FREQUENCY (Hz)
100
–165
PHASE NOISE (dBc
/Hz)
–160
–155
–150
–140
1k
10k
100k
69571234 TA01b
–145
1M
LTC6957-1 (LVPECL)
LTC6957-4 (CMOS)
LTC6957-3
(CMOS)
LTC6957-2 (LVDS)
SINGLE-ENDED SINE WAVE INPUT
AT +7dBm (500mV
RMS
)
FILTA = FILTB = GND
6957 TA01a
SD1
SD2
V
+
GND
OUT2
OUT1
FILTA
FILTB
10nF
50Ω
100MHz
+7dBm
SINE WAVE
10nF
IN
–
IN
+
OCXO
3.3V
TO PLL CHIPS
OR SYSTEM
SAMPLING CLOCKS
0.1µF