Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI 数据表
产品代码
MEGA328P-XMINI
52
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
11.8
Watchdog Timer
11.8.1 Features
•
Clocked from separate On-chip Oscillator
•
3 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
•
Selectable Time-out period from 16ms to 8s
•
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
11.8.2 Overview
ATmega48A/PA/88A/PA/168A/PA/328/P has an Enhanced Watchdog Timer (WDT). The WDT is a timer
counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the
counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR
- Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system
doesn't restart the counter, an interrupt or system reset will be issued.
counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the
counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR
- Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system
doesn't restart the counter, an interrupt or system reset will be issued.
Figure 11-7.
Watchdog Timer
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the
device from sleep-modes, and also as a general system timer. One example is to limit the maximum time
allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System
Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in
case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by
first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe
shutdown by saving critical parameters before a system reset.
device from sleep-modes, and also as a general system timer. One example is to limit the maximum time
allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System
Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in
case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by
first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe
shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode.
With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1
and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed
sequences. The sequence for clearing WDE and changing time-out configuration is as follows:
With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1
and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed
sequences. The sequence for clearing WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic
one must be written to WDE regardless of the previous value of the WDE bit.
2.
Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with
the WDCE bit cleared. This must be done in one operation.
the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The
example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will
occur during the execution of these functions.
example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will
occur during the execution of these functions.
128kHz
OSCILLATOR
O
S
C/2K
O
S
C/4K
O
S
C/8K
O
S
C/16K
O
S
C/32K
O
S
C/64K
O
S
C/128K
O
S
C/256K
O
S
C/512K
O
S
C/1024K
WDP0
WDP1
WDP2
WDP3
WDP1
WDP2
WDP3
WATCHDOG
RESET
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT