Nxp Semiconductors OM11043 数据表
LPC1769_68_67_66_65_64_63
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Product data sheet
Rev. 9.5 — 24 June 2014
28 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
•
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
software at run time.
•
Supports SoftConnect and GoodLink features.
•
While USB is in the Suspend mode, the part can enter one of the reduced power
modes and wake up on USB activity.
modes and wake up on USB activity.
•
Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.
•
Allows dynamic switching between CPU-controlled slave and DMA modes.
•
Double buffer implementation for Bulk and Isochronous endpoints.
8.12.2 USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of a register interface, a serial interface engine, and a DMA
controller. The register interface complies with the OHCI specification.
to the bus. It consists of a register interface, a serial interface engine, and a DMA
controller. The register interface complies with the OHCI specification.
8.12.2.1
Features
•
OHCI compliant.
•
One downstream port.
•
Supports port power switching.
8.12.3 USB OTG controller
USB OTG is a supplement to the USB 2.0 specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the host controller, device controller, and a master-only
I
I
2
C-bus interface to implement OTG dual-role device functionality. The dedicated I
2
C-bus
interface controls an external OTG transceiver.
8.12.3.1
Features
•
Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
1.0a.
•
Hardware support for Host Negotiation Protocol (HNP).
•
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
(SRP).
•
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
(CEA-2011), Rev. 1.0.
8.13 CAN controller and acceptance filters
.
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.