Nxp Semiconductors OM11043 数据表

LPC1769_68_67_66_65_64_63

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2014. All rights reserved.

data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of 
data flowing from the master to the slave and from the slave to the master. In practice, 
often only one of these data flows carries meaningful data.

Maximum SSP speed of 33 Mbit/s (master) or 8 Mbit/s (slave)

Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National 
Semiconductor Microwire buses

Synchronous serial communication

Master or slave operation

8-frame FIFOs for both transmit and receive

4-bit to 16-bit frame

DMA transfers supported by GPDMA

The LPC17xx each contain three I

2

C-bus controllers.

The I

2

C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line 

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and 
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the 
capability to both receive and send information (such as memory). Transmitters and/or 
receivers can operate in either master or slave mode, depending on whether the chip has 
to initiate a data transfer or is only addressed. The I

2

C is a multi-master bus and can be 

controlled by more than one bus master connected to it.

I

2

C0 is a standard I

2

C compliant bus interface with open-drain pins. I

2

C0 also 

supports Fast mode plus with bit rates up to 1 Mbit/s.

I

2

C1 and I

2

C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I

2

C-bus). 

Easy to configure as master, slave, or master/slave.

Programmable clocks allow versatile rate control.

Bidirectional data transfer between masters and slaves.

Multi-master bus (no central master).

Arbitration between simultaneously transmitting masters without corruption of serial 
data on the bus.

Serial clock synchronization allows devices with different bit rates to communicate via 
one serial bus.

Serial clock synchronization can be used as a handshake mechanism to suspend and 
resume serial transfer.

The I

2

C-bus can be used for test and diagnostic purposes.

All I

2

C-bus controllers support multiple address recognition and a bus monitor mode.