Nxp Semiconductors OM11043 数据表

LPC1769_68_67_66_65_64_63

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© NXP Semiconductors N.V. 2014. All rights reserved.

 

[1]

V

DDA

 and VREFP should be tied to V

DD(3V3)

 if the ADC and DAC are not used.

[2]

The ADC is monotonic, there are no missing codes.

[3]

The differential linearity error (E

D

) is the difference between the actual step width and the ideal step width. See 

[4]

The integral non-linearity (E

L(adj)

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after 

appropriate adjustment of gain and offset errors. See 

[5]

The offset error (E

O

) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the 

ideal curve. See 

.

[6]

The gain error (E

G

) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset 

error, and the straight line which fits the ideal transfer curve. See 

.

[7]

The conversion frequency corresponds to the number of samples per second.







E

D

differential linearity error

-

1

-

LSB

E

L(adj)

integral non-linearity

-

1.5

-

LSB

E

O

offset error

-

2

-

LSB

E

G

gain error

-

2

-

LSB

f

clk(ADC)

ADC clock frequency

3.0 V 

 V

DDA

 

 3.6 V

-

-

33

MHz

2.7 V 

 V

DDA

 < 3.0 V

-

-

25

MHz

f

c(ADC)

ADC conversion frequency

3 V 

 V

DDA

 

 3.6 V

-

-

500

kHz

2.7 V 

 V

DDA

 < 3.0 V

-

-

400

kHz