Kingston Technology 3GB, 800MHz, DDR2, CL5 (5-5-5-18), SODIMM (Kit of 1GB + 2GB) KHX6400S2LLK2/3G 数据表
产品代码
KHX6400S2LLK2/3G
Memory Module Specification
Document No. 4805070-001.A00
10/13/08
Page 1
DESCRIPTION:
Kingston's KHX6400S2LLK2/3G is a kit consisting of one 256M x 64-bit 2GB (2048MB) DDR2-
800 plus one 128M x 64-bit 1GB DDR2-800 1GB (1024MB) CL5 SDRAM (Synchronous DRAM)
memory modules. The 2GB module is based on sixteen 128M x 8-bit DDR2 FBGA components and
the 1GB module is based on sixteen 64M x 8-Bit FBGA components. Total kit capacity is 3GB
(3072MB). Each pair has been tested to run at DDR2 800MHz at low latency timing of 5-5-5-18 at
1.8V. The SPDs are programmed to JEDEC latency timing of 5-5-5-18 at 1.8V. Each 200-pin
SODIMM uses gold contact fingers and requires +1.8V. The electrical and mechanical specifica-
tions are as follows:
800 plus one 128M x 64-bit 1GB DDR2-800 1GB (1024MB) CL5 SDRAM (Synchronous DRAM)
memory modules. The 2GB module is based on sixteen 128M x 8-bit DDR2 FBGA components and
the 1GB module is based on sixteen 64M x 8-Bit FBGA components. Total kit capacity is 3GB
(3072MB). Each pair has been tested to run at DDR2 800MHz at low latency timing of 5-5-5-18 at
1.8V. The SPDs are programmed to JEDEC latency timing of 5-5-5-18 at 1.8V. Each 200-pin
SODIMM uses gold contact fingers and requires +1.8V. The electrical and mechanical specifica-
tions are as follows:
FEATURES:
Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 5, 4, 3 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 5-5-5-18 at +1.8V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 5, 4, 3 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 5-5-5-18 at +1.8V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1.180” (30.00mm), double sided component
PERFORMANCE:
Clock Cycle Time (tCK) CL=5
2.5ns (min.) / 8ns (max.)
Row Cycle Time (tRC)
57.5ns (min.)
Refresh to Active/Refresh Command Time (tRFC)
2GB = 127.5ns / 1GB = 105NS
Row Active Time (tRAS)
45ns (min.) / 70,000ns (max.)
Single Power Supply of
+1.8V (+/- .1V)
Power
TBD W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 55
o
C
Storage Temperature
-55
o
C to +125
o
C
T E C H N O L O G Y
KHX6400S2LLK2/3G
3GB (2GB 256M x 64-Bit + 1GB 128M x 64-Bit)
PC2-6400 CL5 200-Pin SODIMM Kit