Intel i3-2328M FF8062701275100 数据表
产品代码
FF8062701275100
Datasheet, Volume 1
33
Interfaces
2.4.2.1.3
Cursors A and B
Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,
and are associated with Planes A and B respectively. These planes support resolutions
up to 256 x 256 each.
and are associated with Planes A and B respectively. These planes support resolutions
up to 256 x 256 each.
2.4.2.1.4
Video Graphics Array (VGA)
VGA is used for boot, safe mode, legacy games, etc. It can be changed by an
application without OS/driver notification, due to legacy requirements.
application without OS/driver notification, due to legacy requirements.
2.4.2.2
Display Pipes
The display pipe blends and synchronizes pixel data received from one or more display
planes and adds the timing of the display output device upon which the image is
displayed. This is clocked by the Display Reference clock inputs.
planes and adds the timing of the display output device upon which the image is
displayed. This is clocked by the Display Reference clock inputs.
The display pipes A and B operate independently of each other at the rate of 1 pixel per
clock. They can attach to any of the display ports. Each pipe sends display data to the
PCH over the Intel Flexible Display Interface (Intel FDI).
clock. They can attach to any of the display ports. Each pipe sends display data to the
PCH over the Intel Flexible Display Interface (Intel FDI).
2.4.2.3
Display Ports
The display ports consist of output logic and pins that transmit the display data to the
associated encoding logic and send the data to the display device (that is, LVDS,
HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are
now repartitioned and driven from the PCH with the exception of the DisplayPort.
associated encoding logic and send the data to the display device (that is, LVDS,
HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are
now repartitioned and driven from the PCH with the exception of the DisplayPort.
2.4.2.4
Embedded DisplayPort*
The Processor Graphics supports the Embedded DisplayPort* (eDP) interface, intended
for display devices that are integrated into the system (such as laptop LCD panel).
for display devices that are integrated into the system (such as laptop LCD panel).
The DisplayPort (abbreviated DP) is different than the generic term display port. The
DisplayPort specification is a VESA standard. DisplayPort consolidates internal and
external connection methods to reduce device complexity, support cross industry
applications, and provide performance scalability. The eDP interface supports link-
speeds of 1.62 Gbps and 2.7 Gbps on 1, 2, or 4 data lanes. The eDP supports -0.5%
SSC and non-SSC clock settings.
DisplayPort specification is a VESA standard. DisplayPort consolidates internal and
external connection methods to reduce device complexity, support cross industry
applications, and provide performance scalability. The eDP interface supports link-
speeds of 1.62 Gbps and 2.7 Gbps on 1, 2, or 4 data lanes. The eDP supports -0.5%
SSC and non-SSC clock settings.
2.4.3
Intel
®
Flexible Display Interface (Intel
®
FDI)
The Intel Flexible Display Interface (Intel
®
FDI) is a proprietary link for carrying display
traffic from the Processor Graphics controller to the PCH display I/Os. Intel
®
FDI
supports two independent channels—one for pipe A and one for pipe B.
• Each channel has four transmit (Tx) differential pairs used for transporting pixel
and framing data from the display engine.
• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS
signaling).
• One display interrupt line input (1-V CMOS signaling).
• Intel
• Intel
®
FDI may dynamically scalable down to 2X or 1X based on actual display
bandwidth requirements.
• Common 100-MHz reference clock.
• Each channel transports at a rate of 2.7 Gbps.
• PCH supports end-to-end lane reversal across both channels (no reversal support
• Each channel transports at a rate of 2.7 Gbps.
• PCH supports end-to-end lane reversal across both channels (no reversal support
required in the processor).