Intel 2127U AV8063801119100 用户手册
产品代码
AV8063801119100
Datasheet, Volume 1
67
Signal Description
6.2
Memory Reference and Compensation Signals
Table 6-3.
Memory Channel B Signals
Signal Name
Description
Direction/
Buffer Type
SB_BS[2:0]
Bank Select: These signals define which banks are selected within
each SDRAM rank.
O
DDR3
SB_WE#
Write Enable Control Signal: This signal is used with SB_RAS# and
SB_CAS# (along with SB_CS#) to define the SDRAM Commands.
O
DDR3
SB_RAS#
RAS Control Signal: This signal is used with SB_CAS# and SB_WE#
(along with SB_CS#) to define the SRAM Commands.
O
DDR3
SB_CAS#
CAS Control Signal: This signal is used with SB_RAS# and SB_WE#
(along with SB_CS#) to define the SRAM Commands.
O
DDR3
SB_DQS[8:0]
SB_DQS#[8:0]
Data Strobes: SB_DQS[8:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SB_DQS[8:0] and its SB_DQS#[8:0] during read and write
transactions.
I/O
DDR3
SB_DQ[63:0]
Data Bus: Channel B data signal interface to the SDRAM data bus.
I/O
DDR3
SB_MA[15:0]
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
O
DDR3
SB_CK[3:0]
SB_CK#[3:0]
SDRAM Differential Clock: Channel B SDRAM Differential clock
signal pair. The crossing of the positive edge of SB_CK and the
negative edge of its complement SB_CK# are used to sample the
command and control signals on the SDRAM.
O
DDR3
SB_CKE[3:0]
Clock Enable: (1 per rank) These signals are used to:
• Initialize the SDRAMs during power-up.
• Power down SDRAM ranks.
• Place all SDRAM ranks into and out of self-refresh during STR.
• Power down SDRAM ranks.
• Place all SDRAM ranks into and out of self-refresh during STR.
O
DDR3
SB_CS#[3:0]
Chip Select: (1 per rank). These signals are used to select particular
SDRAM components during the active state. There is one Chip Select
for each SDRAM rank.
O
DDR3
SB_ODT[3:0]
On Die Termination: Active Termination Control.
O
DDR3
Table 6-4.
Memory Reference and Compensation
Signal Name
Description
Direction/
Buffer Type
SM_VREF
DDR3 Reference Voltage: This signal is used as a reference
voltage to the DDR3 controller.
I
A
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SB_DIMM_VREFDQ
Memory Channel A/B DIMM DQ Voltage Reference: These
output pins are connected to the DIMMs, and are programmed to
have a reference voltage with optimized margin.
The nominal source impedance for these pins is 150
The step size is 7.7 mV for DDR3 (with no load).
The nominal source impedance for these pins is 150
The step size is 7.7 mV for DDR3 (with no load).
O
A