Intel C2530 FH8065401488915 数据表
产品代码
FH8065401488915
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Power Up from G3 State (Mechanical Off)
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
128
Order Number: 330061-002US
Note:
1.
GbE Reference Clock input-pin signals are GBE_REFCLK[P, N] (differential input). If the platform design
does not need the integrated Ethernet Controller to be enabled during the S5 state, the timing
parameter duration is measured only when all standby voltages are valid.
The platform board initiates the power-up sequence by providing the SUS power well
(also called “Always On” and designated by the suffix “A”) supply voltages to the SoC.
To ensure proper SoC operation and avoid damaging the SoC, the standby voltage
groups must be applied to the SoC in a particular order. The order is shown below.
During this sequence, the platform asserts the active-low RSMRST_B signal, powered
by the RTC rail, to the SoC. Also, the platform board must drive the active-high SoC
input COREPWROK low indicating that the Core power well pins do not have their valid
voltage levels. If the platform board does not have a functioning coin-cell battery, these
signals will not be detected by the SoC until the V3P3A voltage is provided to the SoC.
Before advancing to the next step within the sequence, the voltage supplied to the SoC
must be regulated and at a valid voltage level. Voltage levels are measured at the SoC
for valid voltage levels for each voltage group. Here is the
sequence:
1. V1P8A voltage is provided to all V1P8A voltage-group pins of the SoC.
2. V1P0A voltage is provided to all V1P0A voltage-group pins the of SoC.
2. V1P0A voltage is provided to all V1P0A voltage-group pins the of SoC.
— It is permissible for V1P8A and V1P0A to be powered-up at the same time, but
it is best to stagger their ramp-up as indicated here or as V1P0A first, then
V1P8A.
3. Wait for both V1P8A and V1P0A to be regulated and at valid voltage levels.
4. V3P3A voltage is provided to all V3P3A voltage-group pins of the SoC.
4. V3P3A voltage is provided to all V3P3A voltage-group pins of the SoC.
Once V3P3A is valid for a period of time, the platform indicates to the SoC that all
standby voltages are up and valid. It does this by deasserting the RSMRST_B signal.
See
Once V3P3A is valid and the RSMRST_B signal is deasserted, the active-low SoC output
signal PMU_SLP_S45_B becomes valid and asserted (logic-low level) indicating that the
SoC is in the S5 (Soft Off) state. Whenever a logic high level, the RSMRST_B signal
indicates to the SoC that the platform board is providing the SUS power wells with valid
voltage (a.k.a, standby voltage).
The SoC is now in the S5 (Soft Off) state. Only the SUS power well and RTC power well
are active within the SoC.
Table 7-1.
Power-Up SUS Power Well Voltages to S5 State
Sym
Parameter
Min
Max
Units
Note
Fig
t30
RTEST_B deasserted by platform board after
VRTC3P0 voltage valid at SoC pins.
SRTCRST_B deasserted by platform board after
VRTC3P0 voltage valid at SoC pins.
9
-
ms
-
t31
RSMRST_B deasserted by platform board after all
standby voltages are valid and GbE Reference Clock
stable at SoC input pins
10
-
ms
1
-
“SUS Power OK” hard strap value hold time after
RSMRST_B de-asserted by the platform board
400
-
ns
1