Intel C2530 FH8065401488915 数据表
产品代码
FH8065401488915
Volume 2—PCI Express Root Ports (RP)—C2000 Product Family
Architectural Overview
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
226
Order Number: 330061-002US
12.3.4.2
ASPM and ASPM Optionality
The PCI Express Base Specification, Revision 2.1 defines the hardware-initiated power
management of the PCIe link called the Active State Power Management (ASPM). Under
hardware control, the link is in L0 state or an even lower-power L1 link state. ASPM is
totally traffic dependent and is not initiated by the software, but the software enables
or disables ASPM via the Root Ports PCIe Express Capability structure.
The ASPM Optionality Compliance bit in the Link Capabilities Register of each root port,
is used by the software to help determine whether to enable ASPM or whether to run
ASPM-compliance tests.
12.3.4.3
Power Management Event (PME) Signaling
At the device level, the SoC root ports support the D0, D3
HOT
and D3
COLD
device power
management states. In D3
HOT
, the SoC performs a master abort to all configuration
requests targeting the functions downstream of the PCI Express Root Port.
• A Power Management Event (PME) is generated from the D0 power state.
• A PME is generated from D3
• A PME is generated from D3
HOT
power state.
• A PME is generated from D3
COLD
power state.
— The SoC root ports do not support this particular capability, but the capability
bit is set for compliance reasons.
12.3.4.4
Beacon and WAKE# Signaling
At the link level, the PCI Express Base Specification, Revision 2.1 describes two
optional mechanisms used by a components to request the reapplication of main power
(transition to the fully-operative L0 state) when in the low-power L2 Link state:
• Beacon (using in-band signaling)
— Not supported by the SoC root ports.
• WAKE# (using sideband signaling)
— Supported by the SoC root ports through the SoC input signal pin
.
12.3.4.5
No Soft Reset Bit
When this bit is set, the transition of a PCIe Root Port from D3
HOT
state to D0 because
of a Configuration Write Request to the Power State (PS) field of the Root Port
Management Control/Status Register (PMCSR), does not cause an internal soft reset.
12.3.5
PCI Bridge Subsystem Identification Capability
The PCI Bridge Subsystem Vendor ID (Intel
®
Corporation) and additional identification
information are read by the software.