Intel C2530 FH8065401488915 数据表
产品代码
FH8065401488915
Volume 2—SMBus 2.0 Unit 2 - PECI—C2000 Product Family
PECI Over SMBus
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
388
Order Number: 330061-002US
17.6.3
PECI Proxy Command Handling Procedure
A BMC requests read and write PECI proxy commands over the SMBus that are
formatted to conform to the PECI command protocol. The PECI command handler
performs the following on receipt of the SMBus packet:
• Validates that the PECI command is valid.
• Either processes the command locally or forwards the command to other SoC
• Either processes the command locally or forwards the command to other SoC
internal units for processing.
• Repackages the command into the appropriate format upon command completion.
The BMC retrieves the PECI response data by performing the SMBus Block Read
transactions. The number of data bytes returned from the Block Read command on the
SMBus indicates the completion status of the PECI command.
1. If N=1, then only the Status byte is sent with CMB_BUSY bit set (CMD_BUSY=1b).
Indicates that the PECI command transaction is still in progress.
2. If N=2, then both Status and Error Code bytes are sent with CMD_BUSY bit reset
(CMD_BUSY = 0b) and CMD_ERR bit set (CMD_ERR = 1b).
Indicates that the PECI command resulted in an error. Byte 2 contains the Error
Code.
3. If N>2, then both CMD_BUSY and CMD_ERR will be reset (CMD_BUSY = 0b,
CMD_ERR = 0b).
Indicates that the PECI command completed successfully and the read-back
data is valid.
Note:
The BMC should only trigger new PECI command when the previous command is
completed. The SoC does not support posted or multiple commands.
Note:
If the Reset PECI SMBus Command is received, any pending state will be reset. The
initiator would be expected to reissue the last command.