Intel C2530 FH8065401488915 数据表
产品代码
FH8065401488915
Volume 3—Signal Names and Descriptions—C2000 Product Family
PMU Signals
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
604
Order Number: 330061-002US
31.14
PMU Signals
Table 31-17. PMU Signals (Sheet 1 of 2)
Signal Name
I/O
Type
I/O Buffer
Type
Ball
Count
Internal
Resistor
PU/PD
External
Resistor
PU/PD
Power
Rail
Description
CPU_RESET_B/
GPIO_SUS3
O
CMOS_V3P3
1
V3P3A
CPU Reset: Combined CPU
reset for ITP debugger. This is
the logical AND of all core
reset signals. If the
CPU_RESET_B interface is not
used, the signal can be used
as GPIO SUS Port 3.
SUSPWRDNACK/
GPIO_SUS4
O
CMOS_V3P3
1
V3P3A
Active high. Asserted by the
SoC on behalf of the PMC
when it does not require the
SoC suspend well to be
powered. This pin requires a
pull-up to VccSUS. If the
SUSPWRDNACK interface is
not used, the signal can be
used as GPIO SUS Port 4.
PMU_SUSCLK/
GPIO_SUS5
O
CMOS_V3P3
1
V3P3A
Output of the RTC generator
circuit (32.768 kHz). SUSCLK
has a duty cycle that can be
as low as 30% or as high as
70%. If the PMU_SUSCLK
interface is not used, the
signal can be used as GPIO
SUS Port 5.
PMU_SLP_DDRVTT_B/
GPIO_SUS6
O
CMOS_V3P3
1
V3P3A
Controls the power of DRAM.
If the PMU_SLP_DDRVTT_B
interface is not used, the
signal can be used as GPIO
SUS Port 6.
PMU_SLP_S45_B
O
CMOS_V3P3
1
V3P3A
Power plane control. Shuts
power to non-critical systems
when in the S5 (Soft-Off)
state.
PMU_SLP_S3_B
O
CMOS_V3P3
1
V3P3A
Power plane control. Shuts
power to non-critical systems
when in the S3 (Suspend To
RAM) state.
PMU_SLP_LAN_B/
GPIO_SUS7
O
CMOS_V3P3
1
V3P3A
LAN Subsystem Sleep
Control: This active-low
output signal is non-
functional. It is always high
indicating that the PHY device
must be powered. If this
signal is not needed for the
platform board design, it can
be re-configured to function
as GPIO_SUS7.