Intel C2338 FH8065501516761 数据表
产品代码
FH8065501516761
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
319
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
15.4.7.7
Write Disabling to DIMM SPD EEPROM Addresses
Although this controller is not intended to participate in DIMM SPD (Serial Presence
Detect), an attacker connects its data and clock lines to the segment which includes the
SPD EEPROM and mount an attack. To prevent this, a write disable (MCTRL.SPDDIS) is
introduced. If SPDDIS is deasserted, writes are not restricted; however, if SPDDIS is
set then writes to the address range A0h-AEh are blocked and an error is flagged.
Writes to addresses outside the range A0h-AEh are not affected by SPDDIS, and reads
are never affected.
The SPDDIS is read-write-once, and the BIOS Memory Reference Code (MRC) is
expected to set this bit when SPD is complete. Since the SMBus (Host) controller is not
intended for SPD, the BIOS must set its SPDDIS at any time in the boot flow.
15.4.8
SMT as Target
The SMT has a fully-functional target interface for other masters on the SMBus
intending to communicate with SMT. The usage models for this are:
• SMBus ARP Mastering or ARP Target
• Embedded Controller (EC) on SMBus communicating with the SoC
• Embedded Controller (EC) on SMBus communicating with the SoC
The hardware aspect of the target interface is highly generalized. Most transactions are
treated as raw data which are pushed to the firmware, where the firmware transacts
level activity like protocol detection. Acceleration in hardware is limited to interception
of ARP Get-UDID and SMBus Block-Read protocols, which require an immediate return
of data to an external master, and PEC CRC calculation. The other hardware
responsibility is inspection of enough transaction bytes (e.g., target address, command
code, UDID) to ascertain the protocol type and to engage the appropriate hardware
flow.
15.4.8.1
Hardware Buffering for Target Support
The hardware implements a separate 240-bytes buffer to store the bytes it receives as
a target.
The hardware also implements a separate 32-byte buffer which provides generic read
data to external masters for any reads that they perform. This is a generic usage model
in which firmware repeatedly programs the generic read-data buffer register
(GPBRDBUF) with data, programs a MMIO offset (GPBRCTRL) with address, command,
and byte count of how much data is present in the generic read data buffer, and
communicates to the external master the hardware is ready for taking the read (in-
band through SMBus). The external master then launches a block read to the address
programmed with the command, and the hardware provides the byte count and data
bytes associated with it.
Table 15-16. DIMM SPD EEPROM Write-Disable Mechanism
Target Address [7:4]
Target Address [0]
(Read/Write Operation)
SPD Disable Bit
(MCTRL.SPDDIS)
SMBus Behavior
Ah
0 (write)
0 (enabled)
Allow writes to addresses A0-AEh
Ah
0 (write)
1 (disabled)
Deny writes to addresses A0-AEh
and log error (
and log error (
ERRSTS
.SPDWE)
Ah
1 (read)
Any
Allow reads to addresses A0-AEh
!= Ah
Any
Any
Allow writes and reads