Intel C2338 FH8065501516761 数据表
产品代码
FH8065501516761
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
379
Volume 2—SMBus 2.0 Unit 2 - PECI—C2000 Product Family
SMBus Supported Transactions
17.3
SMBus Supported Transactions
In the SoC, the communication between the SMBus controller and the internal PECI
bridge utilizes the SMBus block write and block read transactions as defined in the
SMBus 2.0 specifications.
See
to interpret the SMBus protocol drawing.
S
Start Condition
Sr
Repeated Start Condition
Rd
Read (bit value of 1)
Wr
Write (bit value 0)
X
Shown under a field indicates that field is required
To have the value of ‘x’
A
Acknowledge (this bit position is 0 for an ACK or 1 for a NACK)
P Stop
Condition
PEC
Packet Error Code
…
Continuation of Protocol
Master to Slave
Slave to Master
Figure 17-2. SMBus Protocol
S
Slave Addr
Wr
A
Data Byte
A
P