Intel C2518 FH8065501516710 数据表
产品代码
FH8065501516710
Volume 2—SMBus 2.0 Unit 2 - PECI—C2000 Product Family
PECI Over SMBus
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
382
Order Number: 330061-002US
17.6
PECI Over SMBus
The PECI uses a simple structure of message header and a write-read protocol. All PECI
devices have a command field. The following section describes PECI protocol. Refer to
the RS - Platform Environment Control Interface (PECI) Specification, Revision 3.0 for
details.
17.6.1
PECI Message Header in SMBus
The header conveys to the target device how many bytes master intends to send and
how many it expects to receive back. The first byte of the write data is interpreted as a
command to the device and must be present in all messages. The Ping() command is
the only exception to this rule. Additional bytes are written to convey sub commands or
to send data to the device. A zero value in the Read Length field means no data is read
from the target device. See
for the PECI Message Header. In the figure, N
bytes are to be written to the target and M bytes are to be read back from the target.
In the PECI Message Header, the Address Timing Negotiation (NT) and Message Timing
Negotiation (MT) bits described in RS - Platform Environment Control Interface (PECI)
Specification, Revision 3.0 are not implemented. It is the responsibility of the BMC to
not include these timing bits in the header.
Figure 17-5. PECI Message Header in the SMBus Packet
8
Target Address
1 8
Write Length
8
Read Length
8
Data Bytes [0...N]
00
0
N
M