Intel C2518 FH8065501516710 数据表
产品代码
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
511
Volume 2—General-Purpose I/O (GPIO)—C2000 Product Family
25
General-Purpose I/O (GPIO)
The SoC provides 59 Customer General-Purpose I/O (GPIO) ports. Each port contains a
register that is configured by the platform software, typically the BIOS code, for the
customer application. Associated with each port is an external ball/pin with a number of
driver/receiver options.
• 31 generic 3.3V GPIOs with circuitry in the core power well
• 28 generic 3.3V GPIOs with circuitry in the Suspend (SUS) power well
• 28 generic 3.3V GPIOs with circuitry in the Suspend (SUS) power well
Two of the GPIOs in the SUS power well are always available to the customer to use as
Customer GPIOs. The other SUS and core Customer GPIOs are designed for multiple
uses and may not be available for customer general use if particular system functions
are needed. This multi-use feature of the ball/pins is also called GPIO muxing.
The number of the Customer GPIOs that are multi-use depends on the SKU. Customer
GPIOs not required by a particular SKU can be configured and used as needed.
Some of the Customer GPIOs have pre-defined characteristics that are used only at
reset time. They serve as SoC pin straps that are sampled and retained by the SoC at
that time. This document refers to these as the system functional hard pin straps and
are described in
. Hard pin straps after reset
time, function as the SoC native signals. Once a Customer GPIO is programmed and
enabled, the characteristics of the Customer GPIO override the native function of the
pin.
Figure 25-1. GPIO Covered in This Chapter
I
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Platform Controller Unit
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iLB
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PMC
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SMBus0
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LPC
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SPI
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