Intel E3815 FH8065301567411 数据表
产品代码
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2068
Datasheet
17.19.3
PCS_DWORD2 (pcs_dword2)—Offset 8h
Access Method
Default: 00000000h
21
1h
RW
cri_rxdigfiltsq_enable:
When 1 enables unsquelch based Rx power up in P0 or P0s
20
0h
RW
reg_txfsm_delay_ovrd:
Override enable bit for reg_txfsm_4us_delay
19:16
0h
RW
reg_txfsm_4us_delay_11_8:
Override counter value for 4 us delay in txfsm lane
reset to txbiasen delay
15:14
0h
RW
reg_pclk_rate_1_0:
Override for pclk_rate 00 = gen1 01 = gen2 10 = gen3 11 = GbE
13:12
0h
RW
reg_rate_1_0:
Override for i_rate 00 = gen1 01 = gen2 10 = gen3 11 = GbE
11:9
0h
RW
reg_phymode_2_0:
Override for PHY Mode Selection 000 = PCIE 001 = USB3 010 =
GbE 011 = SATA/SAPIS 100 = Display 101 = DMI 110 = CIO 111 =Reserved
8
0h
RW
reg_modeovren:
When asserted selects register override bits for phymode, datawidth
etc
7:6
1h
RW
reg_datawidth:
Override for Tx data interface width. 00 - Unused 01 - x8/x10 width
(default ) 10 - x16/x20 width 11 - x32/x40 width
5
1h
RW
soft_reset_n:
Active low soft reset override
4
0h
RW
reg_diginelben:
Override for near end digital loopback.
3
0h
RW
reg_digifelben:
Override for far end digital loopback
2
0h
RW
reg_strapgroup_ovrden:
Override Enable for Strap Group
1
0h
RW
reg_yank_timer_done_b_ovrd:
Override for yank_timer_done_b
0
0h
RW
reg_yank_timer_done_b_ovrd_en:
Override Enable for yank_timer_done_b
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword2:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write