Intel N2820 FH8065301616603 数据表
产品代码
FH8065301616603
Datasheet
113
Processor Core
10.4
System Memory Controller
The system memory controller supports DDR3L protocol with up to two 64-bit wide
dual rank channels at data rates up to 1333 MT/s.
dual rank channels at data rates up to 1333 MT/s.
Note:
The memory data rate is fixed for each SKU. Example, for processor supporting
1333 MT/s, only memory devices with 1333 MT/s is supported. For single channel use
cases, Channel 0 must be used.
1333 MT/s, only memory devices with 1333 MT/s is supported. For single channel use
cases, Channel 0 must be used.
10.5
Signal Descriptions
See
for additional details.
The signal description table has the following headings:
•
Signal Name: The name of the signal/pin
•
Direction: The buffer direction can be either input, output, or I/O (bidirectional)
•
Type: The buffer type found in
•
Description: A brief explanation of the signal’s function
Me
mo
ry
Controlle
r
Channel
0
Channel
1
IO
IO
Table 87. Memory Channel 0 DDR3L Signals (Sheet 1 of 2)
Signal Name
Direction
Type
Description
DRAM0_CKP[2,0]
DRAM0_CKN[2,0]
O
DDR3
SDRAM and inverted Differential Clock: (1 pair per Rank)
The differential clock pair is used to latch the command into
The differential clock pair is used to latch the command into
DRAM. Each pair corresponds to one rank on DRAM side.
DRAM0_CS[2,0]#
O
DDR3
Chip Select: (1 per Rank). Used to qualify the command on
the command bus for a particular rank.
DRAM0_CKE[2,0]
O
DDR3
Clock Enable: (power management)
It is used during DRAM power up/power down and Self refresh.
Note: DDR3L uses only DRAM0_CKE[2,0]. DRAM0_CKE[1,3]
It is used during DRAM power up/power down and Self refresh.
Note: DDR3L uses only DRAM0_CKE[2,0]. DRAM0_CKE[1,3]
are not being used for DDR3L.
DRAM0_MA[15:0]
O
DDR3
Memory Address: Memory address bus for writing data to
memory and reading data from memory. These signals follow
common clock protocol w.r.t. DRAM0_CKN, DRAM0_CKP pairs