Intel N2820 FH8065301616603 数据表

Datasheet

705

50 MHz, the 2X OSC clock, is added to increase MIPS for low power MP3 mode. This 
frequency will be supplied by the clock doubler internal to the processor’s Clock Control 
Unit. 

Data CCM, Data cache, Instruction CCM, and Instruction Cache run off of the LPE clock. 
These memories are in a single clock domain.

All Data CCM and Instruction CCM run in the same clock domain.

SSP could be used as either clock masters or clock slaves. Consequently, theses IP 
have dual clock domains.

The first clock domain is clocked from an internal clock (e.g., fabric clock) and is used 
for generic logic like interrupt generation and register access.

The second clock domain drives the serial shift register (either driven internally or 
externally). When driven internally, this clock can be sourced from XTAL clock 25 MHz 
or PLL 19.2 MHz. These clocks are then divided down within the serial interface IP to 
generate the final bit clock for the interface.

After power on, if the SSP input IO clock is in high state, first transition of the clock 
from high to low may be missing due to the processor clock gating logic.

“Frame Master” mode cannot be used when operating as clock slave and “Frame Slave” 
mode cannot be used when operating as clock master.

LPE SSP in master mode uses the SSP CCLK to drive the serial clock. It has very limited 
option to divide CCLK. An M/N divider is added between the 25 MHz clock (XOSC) from 
CCU to each SSP CCLK input as shown in following diagram:

SSP0 Clock

Fabric side: 50/OSC
Link side: Up to 19.2 MHz

SSP0 clock domains

SSP1 Clock

Fabric side: 50/OSC
Link side: Up to 19.2 MHz

SSP1 clock domains

SSP2 Clock

Fabric side: 50/OSC
Link side: Up to 19.2 MHz

SSP2 clock domains