Renesas Stereo System SH7709S 用户手册
Rev. 5.00, 09/03, page 134 of 760
Bit 12—
IIIIR
R
R
RL
LL
LSSSS Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the
IRQLVL bit is 1.
Bit 12: IRLSEN Description
0
Pins
IRLS3
–
IRLS0
disabled
(Initial value)
1
Pins
IRLS3
–
IRLS0
enabled
Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to
the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level.
the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 11: IRQ51S Bit 10: IRQ50S Description
0
0
An interrupt request is detected at IRQ5 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ5 input rising edge
1
0
An interrupt request is detected at IRQ5 input low level
1
Reserved
Bits 9 and 8—IRQ4 Sense Select (IRQ41S, IRQ40S): Select whether the interrupt signal to the
IRQ4 pin is detected at the rising edge, at the falling edge, or at the low level.
IRQ4 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 9: IRQ41S
Bit 8: IRQ40S
Description
0
0
An interrupt request is detected at IRQ4 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ4 input rising edge
1
0
An interrupt request is detected at IRQ4 input low level
1
Reserved
Bits 7 and 6—IRQ3 Sense Select (IRQ31S, IRQ30S): Select whether the interrupt signal to the
IRQ3 pin is detected at the rising edge, at the falling edge, or at the low level.
IRQ3 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 7: IRQ31S
Bit 6: IRQ30S
Description
0
0
An interrupt request is detected at IRQ3 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ3 input rising edge
1
0
An interrupt request is detected at IRQ3 input low level
1
Reserved