Renesas M32R-FPU 用户手册

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M32R-FPU Software Manual (Rev.1.01)

INSTRUCTION SET

2.1 Instruction set overview

Three types of addressing modes can be specified for load/store instructions.

(1) Register indirect

The contents of the register specify the address. This mode can be used by all load/

store instructions.

(2) Register relative indirect

( T h e   c o n t e n t s   o f   t h e   r e g i s t e r )   +   ( 3 2 - b i t   s i g n - e x t e n d e d   1 6 - b i t   i m m e d i a t e   v a l u e )

specifies the address. This mode can be used by all except LOCK and UNLOCK

instructions.

(3) Register indirect and register update

• Adds 4 to register contents [@R+]

The contents of the register specify the memory address, then 4 is added to the
register contents.

(Can only be specified with LD instruction).

• Add 2 to register contents [@R+] [M32R-FPU extended addressing mode]

The contents of the register specify the memory address, then 2 is added to the
register contents.
(Can only be specified with STH instruction).

• Add 4 to register contents [@+R]

The contents of the register is added by 4, the register contents specity the
memory address.
(Can only be specified with ST instruction).

• Subtract 4 to register contents [@–R]

The content of the register is decreased by 4, then the register contents specify

the memory address.

(Can only be specified with ST instruction).

When accessing halfword and word size data, it is necessary to specify the address on

the halfword boundary or the word boundary (Halfword size should be such that the low-

order 2 bits of the address are "00" or "10", and word size should be such that the low

order 2 bits of the address are "00"). If an unaligned address is specified, an address

exception occurs.

When accessing byte data or halfword data with load instructions, the high-order bits are

sign-extended or zero-extended to 32 bits, and loaded to a register.