Renesas R61509V 用户手册
R61509V
Target
Spec
Rev. 0.11 April 25, 2008, page 106 of 181
80-System 8-bit Bus Interface
When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are
transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are
transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB
pins must be fixed at either IOVCC1 or GND level. When transferring the index register setting, make sure
to write upper byte (8 bits).
transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are
transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB
pins must be fixed at either IOVCC1 or GND level. When transferring the index register setting, make sure
to write upper byte (8 bits).
A1
HWR
HOST
PROCESSOR
CSX
RS
WRX
R61509V
8
10
IM[2:0] = 001
CSn
(RDX
(RDX
D15-0
DB17-10
DB9-0
Figure 26 8-bit Interface
DB
17
DB
16
16
DB
15
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
16
DB
15
15
DB
14
DB
13
DB
12
DB
11
DB
10
IB
15
15
IB
14
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Instruction write
Input
Instruction
Instruction code
First transfer
Second transfer
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
17
DB
16
16
DB
15
15
DB
14
DB
13
DB
12
DB
11
DB
10
Device code read / Instruction read
Instruction
Input
First transfer
Second transfer
Note: Device code canot be read out in 3 transfer mode.
Figure 27 8-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)
Note: RAM data cannot be read in the 3-transfer mode.