Intel 440GX 用户手册

Intel

®

 440GX AGPset Design Guide

v

3.7

82371EB (PIIX4E).......................................................................................3-16
3.7.1

PIIX4E Connections.......................................................................3-16

3.7.2

IDE Routing Guidelines..................................................................3-20
3.7.2.1

Cabling..........................................................................3-20

3.7.2.2

Motherboard .................................................................3-20

3.7.3

PIIX4E Power And Ground Pins ....................................................3-22

3.8

PCI Bus Signals ..........................................................................................3-22

3.9

ISA Signals .................................................................................................3-23

3.10

ISA and X-Bus Signals................................................................................3-23

3.11

USB Interface..............................................................................................3-24

3.12

IDE Interface ...............................................................................................3-24

3.13

Flash Design ...............................................................................................3-25
3.13.1 Dual-Footprint Flash Design ..........................................................3-25
3.13.2 Flash Design Considerations .........................................................3-25

3.14

System and Test Signals ............................................................................3-28

3.15

Power Management Signals .......................................................................3-28
3.15.1 Power Button Implementation ........................................................3-30

3.16

Miscellaneous .............................................................................................3-31

3.17

82093AA (IOAPIC)......................................................................................3-32

3.18

Manageability Devices ................................................................................3-33
3.18.1 Max1617 Temperature Sensor ......................................................3-33
3.18.2 LM79 Microprocessor System Hardware Monitor ..........................3-33
3.18.3 82558B LOM Checklist ..................................................................3-34
3.18.4 Wake On LAN (WOL) Header........................................................3-35

3.19

Software/BIOS ............................................................................................3-35
3.19.1 USB and Multi-processor BIOS .....................................................3-35
3.19.2 Design Considerations...................................................................3-36

3.20

Thermals / Cooling Solutions ......................................................................3-36
3.20.1 Design Considerations...................................................................3-36

3.21

Mechanicals ................................................................................................3-36
3.21.1 Design Considerations...................................................................3-37

3.22

Electricals....................................................................................................3-37
3.22.1 Design Considerations...................................................................3-37

3.23

Layout Checklist..........................................................................................3-38
3.23.1 Routing and Board Fabrication ......................................................3-38
3.23.2 Design Consideration.....................................................................3-38

3.24

Applications and Add-in Hardware..............................................................3-38
3.24.1 Design Consideration.....................................................................3-38

4

Debug Recommendations .........................................................................................4-1

4.1

Slot 1 Test Tools ...........................................................................................4-1

4.2

Debug/Simulation Tools................................................................................4-1
4.2.1

Logic Analyzer Interface (LAI)..........................................................4-1

4.2.2

In-Target Probe (ITP).......................................................................4-1

4.2.3

Bus Functional Model (BFM) ...........................................................4-2

4.2.4

I/O Buffer Models .............................................................................4-2

4.2.5

FLOTHERM* Model .........................................................................4-2