Cypress EZ-OTG CY7C67200 用户手册
CY7C67200
Document #: 38-08014 Rev. *G
Page 41 of 78
HSS Enable (Bit 7)
The HSS Enable bit routes HSS to GPIO[15:12].
1: HSS is routed to GPIO
0: HSS is not routed to GPIOs. GPIO[15:12] are free for other
purposes.
purposes.
SPI Enable (Bit 5)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS
Enable bit is set, it overrides and routes the SPI_nSSI pin to
GPIO15.
Enable bit is set, it overrides and routes the SPI_nSSI pin to
GPIO15.
1: SPI is routed to GPIO[11:8]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for
other purposes.
other purposes.
Interrupt 0 Polarity Select (Bit 1)
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.
1: Sets IRQ0 to rising edge
0: Sets IRQ0 to falling edge
Interrupt 0 Enable (Bit 0)
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO
bit on the interrupt Enable register must also be set in order for
this for this interrupt to be enabled.
bit on the interrupt Enable register must also be set in order for
this for this interrupt to be enabled.
1: Enable IRQ0
0: Disable IRQ0
Reserved
All reserved bits must be written as ‘0’.
GPIO 0 Output Data Register [0xC01E] [R/W]
Figure 42. GPIO 0 Output Data Register
Register Description
The GPIO 0 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15
to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.
Reserved
All reserved bits must be written as ‘0’.
GPIO 1 Output Data Register [0xC024] [R/W]
Figure 43. GPIO n Output Data Register
Register Description
The GPIO 1 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15
to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Bit #
15
14
13
12
11
10
9
8
Field
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
15
14
13
12
11
10
9
8
Field
GPIO31
GPIO30
GPIO29
Reserved
GPIO24
Read/Write
R/W
R/W
R/W
-
-
-
-
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
Reserved
Read/Write
R/W
R/W
R/W
R/W
R/W
-
-
-
Default
0
0
0
0
0
0
0
0