Cypress EZ-OTG CY7C67200 用户手册
CY7C67200
Document #: 38-08014 Rev. *G
Page 48 of 78
HSS Transmit Address Register [0xC07C] [R/W]
Figure 54. HSS Transmit Address Register
Register Description
The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block transmit transfer.
HSS Transmit Counter Register
[0xC07E] [R/W]
Figure 55. HSS Transmit Counter Register
Register Description
The HSS Transmit Counter register designates the block byte
length for the next HSS transmit transfer. This register must be
loaded with the word count minus one to start the block
transmit transfer. As each byte is transmitted this register
value is decremented. When read, this register indicates the
remaining length of the transfer.
length for the next HSS transmit transfer. This register must be
loaded with the word count minus one to start the block
transmit transfer. As each byte is transmitted this register
value is decremented. When read, this register indicates the
remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one
giving a maximum value of 0x03FF (1023) or 2048 bytes.
When the transfer is complete this register returns 0x03FF
until reloaded.
giving a maximum value of 0x03FF (1023) or 2048 bytes.
When the transfer is complete this register returns 0x03FF
until reloaded.
Reserved
All reserved bits must be written as ‘0’.
HPI Registers
There are five registers dedicated to HPI operation. In
addition, there is an HPI status port which can be address over
HPI. Each of these registers is covered in this section and are
summarized in
addition, there is an HPI status port which can be address over
HPI. Each of these registers is covered in this section and are
summarized in
.
Bit #
15
14
13
12
11
10
9
8
Field
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Counter...
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Counter
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Table 32.HPI Registers
Register Name
Address
R/W
HPI Breakpoint Register
0x0140
R
Interrupt Routing Register
0x0142
R
SIE1msg Register
0x0144
W
SIE2msg Register
0x0148
W
HPI Mailbox Register
0xC0C6
R/W