Fujitsu MB15E07SL 数据表

14

■

fr

fp

LD

D

O

D

O

t

WU

t

WL

Notes : 

•

  Phase error detection range: –2

π

 to +2

π

•

  Pulses on Do signal during locked state are output to prevent dead zone.

•

  LD output becomes low when phase is t

WU

 or more. LD output becomes high when phase error 

is t

WL

 or less and continues to be so for three cycles or more.

•

  t

WU

 and t

WL

 depend on OSC

IN

 input frequency. 

t

WU 

> 2/fosc (s) (e. g. t

WU

 > 156.3 ns, fosc = 12.8 MHz)

t

WU 

< 4/fosc (s) (e. g. t

WL

 < 312.5 ns, fosc = 12.8 MHz)

•

  LD becomes high during the power saving mode (PS = “L”).

[FC = “H”]

[FC = “L”]