Fujitsu MB15E07SL 数据表

8

■

The divide ratio can be calculated using the following equation:

f

VCO

 = [(M 

×

 N) + A] 

×

 f

OSC

 

÷

 R   (A < N)

f

VCO

: Output frequency of external voltage controlled oscillator (VCO)

N

: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A

: Preset divide ratio of binary 7-bit swallow counter (0 

≤

 A 

≤

 127)

f

OSC

: Output frequency of the reference frequency oscillator

R

: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

M

: Preset divide ratio of modulus prescaler (32 or 64)

Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:

H

For the programmable reference divider

L

For the programmable divider

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

C
N

T

R

1

R

2

R

3

R

4

R

5

R

6

R

7

R

8

R

9

R

10

R

11

R

12

R

13

R

14

SW

FC LDS CS

MSB

Data Flow

CNT

: Control bit

[Table 1]

R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383)

[Table 2]

SW

: Divide ratio setting bit for the prescaler (32/33 or 64/65)

[Table 5]

FC

: Phase control bit for the phase comparator

[Table 8]

LDS

: LD/f

OUT

 signal select bit

[Table 7]

CS

: Charge pump current select bit

[Table 6]

Note: Start data input with MSB first.

LSB