Elixir DDR2 UDIMM 1024MB M2Y1G64TU88D5B-AC 用户手册
产品代码
M2Y1G64TU88D5B-AC
M2Y1G64TU88D0B / M2Y2G64TU8HD0B / M2Y1G64TU88D4B / M2Y2G64TU8HD4B / M2Y1G64TU88D4B
M2Y1G64TU88D5B / M2Y2G64TU8HD5B / M2Y1G64TU88D6B / M2Y2G64TU8HD6B
M2Y1G64TU88D7B
M2Y1G64TU88D5B / M2Y2G64TU8HD5B / M2Y1G64TU88D6B / M2Y2G64TU8HD6B
M2Y1G64TU88D7B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.2
14
10/2008
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(T
CASE
= 0 °C ~ 85 °C; V
DDQ
= 1.8V ± 0.1V; V
DD
= 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
PC2-5300
PC2-6400
Unit
Min.
Max.
Min.
Max.
T
ck
Clock Cycle Time (Average)
3000
8000
2500
8000
ps
T
ch
CK high-level width (Average)
0.48
0.52
0.48
0.52
T
ck
T
cl
CK low-level width (Average)
0.48
0.52
0.48
0.52
T
ck
WL
Write command to DQS associated clock edge
RL-1
RL-1
Nck
T
dqss
Write command to 1
st
DQS latching transition
-0.25
0.25
-0.25
0.25
T
ck
T
dss
DQS falling edge to CK setup time (write cycle)
0.2
-
0.2
-
T
ck
T
dsh
DQS falling edge hold time from CK (write
cycle)
cycle)
0.2
-
0.2
-
T
ck
T
dqsl,(H)
DQS input low (high) pulse width (write cycle)
0.35
-
0.35
-
T
ck
T
wpre
Write preamble
0.35
-
0.35
-
T
ck
T
wpst
Write postamble
0.4
0.6
0.4
0.6
T
ck
T
is
Address and control input setup time
200
-
175
-
ps
T
ih
Address and control input hold time
275
-
250
-
ps
T
ipw
Input pulse width
0.6
-
0.6
-
T
ck
T
ds
DQ and DM input setup time (differential data
strobe)
strobe)
100
-
50
-
ps
T
dh
DQ and DM input hold time(differential data
strobe)
strobe)
175
-
125
-
ps
T
dipw
DQ and DM input pulse width (each input)
0.35
-
0.35
-
T
ck
T
ac
DQ output access time from CK/
-450
450
-400
400
ps
T
dqsck
DQS output access time from CK/
-400
400
-350
350
ps
T
hz
Data-out high-impedance time from CK/
-
t
AC
max
-
t
ACmax
ps
T
lz(DQS)
DQS low-impedance time from CK/
t
AC
min
t
AC
max
t
ACmin
t
ACmax
ps
T
lz(DQ)
DQ low-impedance time from CK/
2t
AC
min
t
AC
max
2t
AC
min
t
AC
max
ps
T
dqsq
DQS-DQ skew (DQS & associated DQ signals)
-
240
-
200
ps
T
hp
Minimum half clk period for any given cycle;
defined by clk high (T
defined by clk high (T
ch)
or clk low (T
cl
) time
Min(T
ch(abs),
T
cl(abs)
)
-
Min(T
ch(abs),
T
cl(abs)
)
-
ps
T
qhs
Data hold Skew Factor
-
340
-
300
ps
T
qh
Data output hold time from DQS
t
HP
– t
QHS
-
T
hp
– T
qhs
-
ps
T
rpre
Read preamble
0.9
1.1
0.9
1.1
T
ck
T
rpst
Read postamble
0.4
0.6
0.4
0.6
T
ck
T
rrd
Active bank A to Active bank B command
7.5
-
7.5
-
ns
T
faw
Four Activate Window for 1KB page size
products
products
37.5
-
35
-
ns
T
ccd
to
2
2
Nck
T
wr
Write recovery time without Auto-Precharge
15
-
15
-
ns
T
dal
Auto precharge write recovery + precharge time
WR+tnRP
-
WR+tnRP
-
Nck
T
wtr
Internal write to read command delay
7.5
-
7.5
-
ns
T
rtp
Internal read to precharge command delay
7.5
7.5
ns
T
cke
CKE minimum pulse width
3
3
Nck
T
xsnr
Exit self refresh to a Non-read command
T
rfc
+10
-
T
rfc
+10
ns
T
xsrd
Exit self refresh to a Read command
200
-
200
Nck
T
xp
Exit precharge power down to any Non- read
command
command
2
-
2
-
Nck