Silicon Image Drive SSD-P08G(I)-3521 数据表
ATA R
EGISTERS
SSD-P
XXX
(I)-3521 D
ATA
S
HEET
S
ILICON
S
YSTEMS
P
ROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
3521P-02DSR
P
AGE
57
F
EBRUARY
2, 2009
D
EVICE
C
ONTROL
R
EGISTER
The Device Control register is used to control the interrupt request and issue
ATA software resets.
ATA software resets.
Table 44: Device Control Register
Operation
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Write
-
-
-
-
1
SRST
nIEN
0
Bit(s)
Description
7-4
Reserved bits.
3
Always set to 1.
2
Software Reset (SRST).
When set, resets the ATA software.
1
Interrupt Enable (nIEN).
When set, device interrupts are disabled.
There is no function in the memory-mapped mode.
0
Always set to 0.